Makefile

I am trying to write makefile after going through some tutorial here:
http://www.gnu.org/software/make/manual/make.html#Wildcard-Examples

My objective is to create makefile which reads the files from specified directories using VPATH variable and vpath directive, but i am getting error

gcc -o foo
gcc: no input files
make: *** [foo] Error 1

My directory structure is as below:

+Project (Makefile)
+Libraries(some .c files)
+Application(some .c files)
+Headers(some .h files)

where Project is a parent directory which has Makefile and other directories like Libraries, Application and Headers.

I would like to compile files in those directories by using a makefile present in Project Directory.

My Makefile is as below:

VPATH = Lib:App:Head
#vpath %.c Lib:Head:App
objs := $(patsubst %.c,%.o,$(wildcard *.c))
foo: $(objs)
gcc -o foo $(objs)


Please help.

wildcard doesn't search vpath, it's only used for resolving target:dependency lookups.

Try
objs := $(patsubst %.c,%.o,$(wildcard Lib/*.c))
objs += $(patsubst %.c,%.o,$(wildcard App/*.c))
objs += $(patsubst %.c,%.o,$(wildcard Head/*.c))

But , the link provided says if the file is not found in current directory, make will search the paths provide in VPATH or vpath.
And also if i want to compile all the files with -Wall, what is the correct place to add and how.

> But , the link provided says if the file is not found in current directory, make will search the paths provide in VPATH or vpath.
Yes, but only for
foo.o : foo.c
type rules.

If foo.c isn't in the current directory, then the directories in VPATH are searched.

VPATH isn't used for everything.
In fact, wildcard searches on VPATH could result in an uncontrollable mess of 100's of files you really didn't expect.

IMO, you're trying to bend the tool into a shape it wasn't designed for. There are ways of doing multi-level makes - read up on them.

Thanks, I am actually going through various methods used , but i could not find any makefile which deals with multiple directories.