December 22nd, 2006, 07:47 AM
Below is a question in my class and its one of the only ones that has me stumped. Below is the question.
Suppose on a certain machine there is a special PC-increment adder. When passed the contents of the program counter, this adder adds the instruction size and returns the result. Describe how this adder could be used to speed up the fetch/execute cycle. What factor limits the possible speed increase?
Here is what I do know:
I understand how a fetch execute process works with the instruction being stored in RAM and that the program counter is a special register holding the list of the next instructions to be processed. or stated differently the program counter keeps track of the CPU's place in the current program. After an instruction is fetched, the PC is incremented by the length of the instruction SIZE in terms of memory units. Often the instruction to be fetched must be retrieved from relatively slow memory, causing the CPU to stall while waiting for the instruction to be returned.
Here is where I am stuck what does an increment adder have to do with speeding up the above process?
My best guess was it is because the CPU can automatically know how many registries to reserve to stay open for the instructions instead of having to open resources each time it encounters the next instruction in the program counter. but then that didn't really make sense either because I didn't think a cpu could reserve registries or would even want to.
December 22nd, 2006, 06:50 PM
Think about how instructions get separated to get tossed into a pipeline.
Assuming avariable instruction length architecture, you gotta know where they start in memory before you can the start of an instruction right?
Branch predictors obviously want to peeking ahead at the incoming stream too.
Cache line load logic needs to know when the stream is about to cross a line boundary and a if a new line needs to be fetched.