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    Makefile For Multiple Subdirectories


    Hi I'm Very New To Programming!

    I have Some 5 Directories And Inside Every Directory There Are 3 More Directories INC, SRC & OBJ.

    INC -> Contains Only One Header File [*.h]
    SRC -> Contains *.c & *.h Files
    OBJ -> Must Contain Object Files

    A - INC
    - SRC
    - OBJ
    - Makefile

    Output : A.a

    B - INC
    - SRC
    - OBJ
    - Makefile

    Output: B.a

    Main.c
    Makefile [ MainMakeFile]
    This Make File SHud Generate Executable Using A.a & B.a


    I Need To Write A Makefile In All Directories To Do Compilation And Create An Archive[*.a] From Object Files In OBJ Directory.

    I Have A *.c File With main() Which Is The InputFile To The Main MakeFile.The Main MakeFile Must Take All Archives [*.a] From All Directories To Produce One Main Executable.


    One More Thing I Dont Want To Use Full Path Of Header Files In *.c Files.

    Looking For A Response!

    Regards
    JohnnyMalvia
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    Something like this perhaps:

    Common Settings file (include.mk)
    =========================
    Code:
    CC = gcc
    CFLAGS = -Wall -O2 ... rest of compiler options ....
    INC_DIRS = -I/path/to/subdir1/inc -I/path/to/subdir2/inc
    LIB_DIRS = -L/path/to/extra/lib1 -L/path/to/extra/lib2
    LIBS = -llib1 -llib2 ... rest of optional libs
    TOP LEVEL MAKEFILE
    ==================
    Code:
    include ./include.mk
    DIRS += subdir1
    DIRS += subdir2
    DIRS += subdir3
    ...
    
    all:
            for dir in $(DIRS); do (cd $$dir; make $1 || exit 1) || exit 1; done
    SUB-DIRECTORY MAKEFILE
    ====================
    Code:
    include ../include.mk
    
    OBJS = src_file1.o src_file2.o src_file3.o
    INC_LOCAL = ....whatever....
    
    all: $(OBJS)
            ar -r $@ $(OBJS)
    
    .c.o::
            $(CC) -c $(CFLAGS) $(CPPFLAGS) $(INC_LOCAL) $(INC_DIRS) $< -o $@
    
    clean:
          /bin/rm *.o
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