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    Makefile - Linux


    Is it possible to compile only the latest updated c file in the current working directory using makefile ?

    To be more clear.

    I have a directory "work". Inside this directory I have p1.c, p2.c , p3.c etc.

    Just assume I will change code inside p2.c. If I enter "make" I want only p2.c to be compiled and create a.out. Is this possible ?
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    Yes, that is what makefiles are supposed to do - minimise the amount of rebuild effort.
    If you dance barefoot on the broken glass of undefined behaviour, you've got to expect the occasional cut.
    If at first you don't succeed, try writing your phone number on the exam paper
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    Originally Posted by salem
    Yes, that is what makefiles are supposed to do - minimise the amount of rebuild effort.
    Can you guide me how to achieve this ?
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    Have you discovered web search engines yet?

    make manual
    If you dance barefoot on the broken glass of undefined behaviour, you've got to expect the occasional cut.
    If at first you don't succeed, try writing your phone number on the exam paper
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    Originally Posted by salem
    Have you discovered web search engines yet?

    make manual
    Was able to do it using ls.
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    Sympathetic


    Reference, you should have found this.

    Here's a gnu makefile that solves your problem. With this I can
    $ make a.out p p1
    where a.out, p, and p1 are all the same program by different name.

    a.out is the default output name, I didn't have to specify -o$@

    p is a target not mentioned in the prerequisites so I need to write an explicit rule.

    Finally, since p1 is a prerequisite the implicit rule takes care of everything for me. I usually try to arrange my project to avoid writing explicit rules.

    Code:
    override CFLAGS:= -Wall $(CFLAGS)
    
    names := p1 p2 p3
    objects := $(addsuffix .o,$(names))
    
    a.out: $(objects)
    	$(CC) $(LDFLAGS) $+ $(LOADLIBES) $(LDLIBS)
    
    p: $(objects)
    	$(CC) $(LDFLAGS) $+ $(LOADLIBES) $(LDLIBS) -o $@
    
    p1: $(objects)
    Usually in a makefile one needs the list of names repeatedly with various suffixes. In this I've shown how to write the list of names once and use the various functions to modify them as needed. You'll need only one of the 3 rules. They're examples.
    Last edited by b49P23TIvg; November 9th, 2012 at 08:36 AM.
    [code]Code tags[/code] are essential for python code and Makefiles!
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    Solution


    I keep writing c code snippets in a directory with names p1.c , p2.c and so on. Each c file will be having main function.I wanted a Makefile which finds out by itself which is the last modified file and compile it. I don't wanted to manually enter the name of c file in Makefile.

    I was able to do it by

    Code:
    SRC=$(shell ls -rt | tail -1)
    test: $(SRC)
            gcc -o test $(shell ls -rt | tail -1)
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    Then you pretty much missed the point of
    Code:
    target: dependency
            rule
    That is, if any of dependency is NEWER than target, then execute rule.

    So read b49P23TIvg's reply, and the make manual page, to try and come up with a list of your source files expressed in the above style.
    If you dance barefoot on the broken glass of undefined behaviour, you've got to expect the occasional cut.
    If at first you don't succeed, try writing your phone number on the exam paper
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    Here is a set of web-based tutorials for creating and using make files.

    http://linuxgazette.net/issue83/heriyanto.html
    http://www.codercaste.com/2009/11/10/how-to-create-and-use-makefiles/
    http://muquit.com/muquit/software/genmake/genmake.html

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